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3-channel digital potentiometer with nonvolatile memory adn2860 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 3 channels: dual 512 -position single 128-pos i tion 25 k? or 25 0 k ? full-scal e resi stance low temperature coefficient: potentiometer divider 15 ppm/c rheostat mode 35 ppm/ c nonvolatile me mory retains w i per settings permanent me mory write protection linear increment/decrement 6 db increme n t/decrement i 2 c-compatible serial interf ace 2.7 v to 5.5 v si ngle-supply op eration 2.25 v to 2 .7 5 v dua l -suppl y o p eratio n power-on reset time 256 byte s gene ral-purpose us er eeprom 11 bytes rdac user eeprom gbic and sfp c o mpliant eeprom 100-y ear t y pical dat a retenti o n at t a = 55 c applic ati o ns laser dio d e dri v ers optical amplifiers tia gain settin g tec controller temperature s e tpoint func tio n a l block di agram a0 w0 b0 a1 w1 b1 a2 w2 b2 a0 w0 b0 a0 w0 b0 a1 w1 b1 a1 w1 b1 a2 w2 b2 a2 w2 b2 rdac0 rdac0 r e gister rdac1 r e gister rdac2 r e gister 9 bits rdac1 9 bits rdac2 7 bits data control command decode logic address decode logic decode logic power-on reset i 2 c serial interface 32 bytes rdac eeprom 256 bytes user eeprom v dd v ss dgnd scl sda ad0 ad1 a0_ee a1_ee reset wp 03615- 0- 001 fi g u r e 1 . general description the adn2860 p r o v ides d u al 5 12-p o si tio n an d a sin g le 128-p o si tio n dig i tal l y co n t r o l l ed va r i ab le r e sis t o r s 1 (vr) in a sin g le 4 mm 4 mm lf csp p a cka g e. this d e vic e p e r f o r m s t h e s a me ele c t r o n ic ad j u st m e n t f u nc t i o n as a p o t e n t io m e t e r , t r i m me r , or v a r i abl e re s i stor . e a ch v r of f e r s a c o m p l e tely p r og ra mma b l e val u e o f r e sis t a n ce b e tw e e n t h e a t e r m inal and th e wi pe r o r th e b t e rm i n al a n d th e wi pe r . th e f i x e d a - t o - b t e r m inal r e sis t an ce o f 25 k? o r 250 k? has a 1 % c h a n ne l-t o - ch an nel m a tc h i ng to l e r a nc e a n d a nom i n a l te m p e r a t u r e co ef f i cien t o f 35 p p m /c. w i pe r posi ti o n p r ogr a mm in g , ee p r o m 2 r e ading, and eepr o m wr i t i n g a r e cond uc te d v i a t h e st a n d a r d 2- wir e i 2 c in ter f ace . p r e - v i o u s / d e fa ul t wi pe r pos i ti o n s e t t i n g s c a n be s t o r ed i n m e m o r y , a nd r e f r esh e d up o n sy ste m p o w e r - u p . a d di tio n al f e a t ur es o f th e adn2860 in c l ude p r ep r o g r a m m e d l i n e a r a n d l o ga ri th m i c in cr em en t / d e cr em e n t wi pe r c h a n g i n g . the ac t u al r e sist o r t o lera n c es a r e s t o r ed in eepr o m s o tha t t h e ac t u a l e nd- to -e nd r e sist an ce is k n o w n, w h ich i s va l u a b le fo r ca lib r a t ion i n p r e c isio n a p pli c a t i o n s . the adn2860 eep r o m, c h a n n e l r e s o l u tio n , and p a c k a g e size co nf o r m t o gb i c a nd s f p sp ecif ica t io n s . th e ad n2860 is a v a i la b l e in a 4 mm 4 mm 24 -lead lfcs p p a c k a g e . al l p a r t s a r e gua r a n t e e d to o p era t e o v er t h e ext e nde d in d u s t r i al t e m p era - t u r e ra n g e o f ?40c t o +85c. 1 the terms progra mmabl e res i s t or, variabl e res i s t or, rdac , and d i gital po te ntio m e t e r are us ed inte rchange a bl y. 2 the te rms no nvo l a t il e me mo ry, ee mem , and ee p r om are use d inte rchange a bl y.
adn2860 rev. 0 | page 2 of 20 table of contents electrical characteristics ................................................................. 3 electrical characteristics ................................................................. 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 interface descriptions .................................................................... 10 i 2 c interface ................................................................................ 10 eeprom interface..................................................................... 11 rdac i 2 c interface.................................................................... 12 theory of operation ...................................................................... 15 linear increment and decrement commands ...................... 15 logarithmic taper mode adjustment ( 6 db/step) .............. 15 using additional internal nonvolatile eeprom .................. 16 digital input/output configuration........................................ 16 multiple devices on one bus ................................................... 16 level shift for bidirectional communication ........................ 16 terminal voltage operation range ......................................... 16 power-up sequence ................................................................... 17 layout and power supply biasing ............................................ 17 rdac structure.......................................................................... 17 calculating the programmable resistance ............................. 17 programming the potentiometer divider............................... 18 applications..................................................................................... 19 laser diode driver (ldd) calibration................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 7/04revision 0: initial version
adn2860 rev. 0 | page 3 of 20 electrical characteristics single supply: v dd = 2.7 v to 5.5 v and ?40c < t a < +85c, unless otherwise noted. dual supply: v dd = +2.25 v or +2.75 v, v ss = ?2.25 v or ?2.75 v and ?40c < t a < +85c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode resistor differential nonlinearity 2 r-dnl r wb , 7-bit channel ?0.75 +0.75 lsb r wb , 9-bit channels ?2.5 +2.5 lsb resistor integral nonlinearity 2 r-inl r wb , 7-bit channel ?0.5 +0.5 lsb r-inl r wb , 9-bit channels, v dd = 5.5 v ?2.0 +2.0 lsb r-inl r wb , 9-bit channels, v dd = 2.7 v ?4.0 +4.0 lsb resistance temperature coefficent (?r wb /r wb )/?t 10 6 35 ppm/c wiper resistance r w v dd = 5 v, i w = 1 v/r wb 100 150 ? v dd = 3 v, i w = 1 v/r wb 250 400 ? channel resistance matching ?r ab1 /?r ab2 ch 1 and 2 r wb , dx = 0x1ff 0.1 % nominal resistor tolerance ?r ab /r ab dx = 0x3ff ?15 +15 % dc characteristics, potentiometer divider mode differential nonlinearity 3 dnl 7-bit channel ?0.5 +0.5 lsb dnl 9-bit channels ?2.0 +2.0 lsb integral nonlinearity 3 inl 7-bit channel ?0.5 +0.5 lsb inl 9-bit channels ?2.0 +2.0 lsb voltage divider temperature coefficent (?v w /v w )/?t 10 6 code = half-scale 15 ppm/c full-scale error v wfse 7-bit channel/9-bit channel, code = full-scale ?1/?2.75 0/0 lsb zero-scale error v wzse 7-bit channel/9-bit channel, code = zero-scale 0/0 1/2.0 lsb resistor terminals terminal voltage range 4 v a, b, w v ss v dd v capacitance 5 ax, bx c a,b f = 1 khz, measured to gnd, code = half-scale 85 pf capacitance 5 wx c w f = 1 khz, measured to gnd, code = half-scale 95 pf common-mode leakage current 5, 8 i cm v w = v dd /2 0.01 1 a digital inputs and outputs input logic high v ih v dd = 5 v, v ss = 0 v 2.4 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 2.1 v input logic low v il v dd = 5 v, v ss = 0 v 0.8 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 0.6 v output logic high (sda) v oh r pull-up = 2.2 k? to v dd = 5 v, v ss = 0 v 4.9 v output logic low v ol r pull-up = 2.2 k? to v dd = 5 v, v ss = 0 v 0.4 v wp leakage current i wp wp = v dd 9 a a0 leakage current i a0 a0 = gnd 3 a
adn2860 rev. 0 | page 4 of 2 0 p a r a m e t e r s y m b o l c o n d i t i o n s m i n typ 1 m a x u n i t input leakage current (excluding wp and a0) i i v in = 0 v or v dd 1 a input capacitance 5 c i 5 pf power suppli e s single-supply p o wer range v dd v ss = 0 v 2.7 5 . 5 v dual-supply power range v dd /v ss 2.25 2 . 7 5 v positive supply current i dd v ih = v dd or v il = gnd, v ss = 0 v 5 1 5 a negative supply current i ss v ih = v dd or v il = gnd, v dd = 2.5 v, v ss = ?2.5 v ? 5 ? 1 5 a eemem data st oring mode current i dd_st ore v ih = v dd or v il = gnd 35 ma eemem data re storing mode current i dd_rest ore v ih = v dd or v il = gnd 2.5 ma power dissi pati on 6 p diss v ih = v dd = 5 v or v il = gnd 2 5 7 5 w power supply s e nsitivity 5 p ss ? v dd = 5 v 10% 0 . 0 1 0 . 0 2 5 % / % s e e the f o o tno t e s a f t e r t a bl e 2. 03615-0-015 sd a scl ps sp t 1 t 2 t 3 t 8 t 8 t 9 t 4 t 5 t 7 t 10 t 6 fi g u r e 2 . i 2 c ti mi ng d i ag r a m
adn2860 rev. 0 | page 5 of 20 electrical characteristics single supply: v dd = 3 v to 5.5 v and ?40c < t a < +85c, unless otherwise noted. dual supply: v dd = +2.25 v or +2.75 v, v ss = ?2.25 v or ?2.75 v and ?40c < t a < +85c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dynamic characteristics 5, 7 bandwidth ?3 db bw v dd /v ss = 2.5 v, r ab = 25 k?/250 k? 125/12 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = v dd , v b = 0 v, v w = 0.50% error band, code = 0x000 to 0x100, r ab = 25 k?/250 k? 4/36 s resistor noise spectral density e n_wb r ab = 25 k?/250 k?, t a = 25c 14/45 nvhz digital crosstalk c t v a = v dd , v b = 0 v, measure vw with adjacent rdac making full-scale change ?80 db analog crosstalk c at signal input at a0 and measure output at w1, f = 1 khz ?72 db interface timing characteristics (apply to all parts) 8, 9 scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period the first clock pulse is generated 600 ns t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su;sta setup time for start condition t 5 600 ns t hd;dat data hold time t 6 900 ns t su;dat data setup time t 7 100 ns t r rise time of both sda and scl signals t 8 300 ns t f fall time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 600 ns eemem data storing time t eemem_store 26 ms eemem data restoring time at power-on t eemem_restore1 360 s eemem data restoring time on restore t eemem_restore2 360 s command or reset operation eemem data rewritable time t eemem_rewrite 540 s flash/ee memory reliability endurance 10 100 kcycles data retention 11 55c 100 years 1 typical represents average readings at 25c, v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. 4 resistor terminals a, b, w have no limitations on polari ty with respect to each other. 5 guaranteed by design and not subject to production test. 6 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 7 all dynamic characteristics use v dd = 5 v. 8 bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the f astest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 9 see the timing diagram for location of measured values. 10 endurance is qualified to 100,000 cycles as per jedec std. 22 metho d a117 and measured at ?40c, +25c, and +85c, typical end urance at 25c is 700,000 cycles. 11 retention lifetime equivalent at junction temperature (t j ) = 55c as per jedec std. 22, method a117. retention lifetime based on an activation energy of 0.6ev derates with junction temperature.
adn2860 rev. 0 | page 6 of 2 0 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g v dd to gnd ?0.3 v, +7 v v ss to gnd +0.3 v, ?7 v v dd to v ss 7 v v a , v b , v w to g n d v ss ? 0.3 v, v dd + 0.3 v i a , i b , i w intermittent 1 2 0 m a c o n t i n u o u s 2 m a digital inputs and output vo ltage to gnd ?0.3 v, v dd + 0.3 v operating temperature range 2 ?40c to +85c maximum junction temperature (t j max) 150c storage temperature ?65c to +150c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c t h ermal resista n ce junction-to- ambient ja , l f c s p - 2 4 3 2 c / w _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___ __ __ __ __ __ __ __ __ __ __ __ __ ___ 1 i n cl ud es pr ogramming of non v ol a t il e memor y . 2 m a ximum t e r minal cur r en t is b o unde d b y the maximum cur r e n t hand l i ng o f the s w it ches, maxi m um pow e r d i ss ip a t ion of the pack age , and maximum ap pl ied v o l t age acr o s s an y t w o of the a, b , and w t e r minal s a t a giv e n r e si st a n c e . s t r e s s es g r e a t e r t h a n t h os e lis t e d under a b s o l u te m a xi m u m r a tin g s m a y ca use pe rm a n en t d a ma g e t o t h e devi ce . t h is i s a st re ss r a t i n g on l y and f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or an y ot he r c o nd it i o n s ab ove t h o s e i n d i c a te d i n t h e op e r a t i o n a l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
adn2860 rev. 0 | page 7 of 2 0 pin conf igura t ion and fu nction descriptions pin 1 indicator nc = no connect 1 reset 2 wp 3 scl 4 sda 5 dgnd 6 v ss v dd 15 a0 16 17 test3 (nc) 18 test2 (nc) 14 w0 13 b0 7 a 2 8 w 2 9 b 2 1 1 w 1 1 2 b 1 1 0 a 1 2 1 a 1 _ e e 2 2 a 0 _ e e 2 3 a d 1 2 4 a d 0 2 0 t e s t 0 ( n c ) 1 9 t e s t 1 ( n c ) top view (not to scale) ad2860 03615-0-014 f i gure 3. pin config ur ation ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic description 1 reset resets the scrat c hpad register with current contents of the eemem register. f a ctory defaults t o midscale before any programmi ng. 2 wp write protect. when active lo w, wp prevents any ch anges to the pre s ent register co ntents, except t h at reset and commands 1 and 8 still refresh the rdac register from eem em. 3 scl serial input register clock. shifts in one bit at a time on the positi ve cloc k edges. 4 sda serial data inpu t. shifts in one bit at a time on th e positive clk e d ges. the msb i s loaded first. 5 dgnd ground. logic ground reference. 6 v ss negative supply. connect to 0 v for single-sup ply app l ication s . 7 a2 a terminal of rdac2. 8 w2 wiper terminal of rdac2. 9 b2 b terminal of rdac2. 10 a1 a terminal of rdac1. 11 w1 wiper terminal of rdac1. 12 b1 b terminal of rdac1. 13 b0 b terminal of rdac0. 14 w0 wiper terminal of rdac0. 15 a0 a terminal of rdac0. 1 6 v dd positive power s u pply. 17 test3 test pin 3. do not connect. 18 test2 test pin 2. do not connect. 19 test1 test pin 1. do not connect. 20 test0 test pin 0. do not connect. 2 1 a 1 _ e e i 2 c device addr ess 1 for eemem . 2 2 a 0 _ e e i 2 c device addr ess 0 for eemem . 2 3 a d 1 i 2 c device addr ess 1 for rdac. 2 4 a d 0 i 2 c device addr ess 0 for rdac.
adn2860 rev. 0 | page 8 of 2 0 typical perf orm ance cha r acte ristics ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 inl ( l sb) 256 19 2 64 1 2 8 0 320 384 44 8 512 code (decimal) 03615-0-002 t a = ? 40c, +25c, +85c superimposed v dd = 5v f i g u re 4. inl 9- bit r d a c ?1.50 ?1.00 ?0.50 ?0.75 ?1.25 0 ?0.25 dnl (ls b ) 0.50 0.25 1.00 0.75 1.50 1.25 256 19 2 64 1 2 8 0 320 384 44 8 512 code (decimal) 03615-0-003 t a = ? 40c, +25c, +85c superimposed v dd = 5v f i g u re 5. dn l 9-b i t r d a c ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 r-inl (ls b ) 256 19 2 64 1 2 8 0 320 384 44 8 512 code (decimal) 03615-0-004 t a = ? 40c, +25c, +85c superimposed v dd = 5v f i g u re 6. r-inl 9- bit r d a c ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 r-dnl (ls b ) 256 19 2 64 1 2 8 0 320 384 44 8 512 code (decimal) 03615-0-005 t a = ? 40c, +25c, +85c superimposed v dd = 5v fi g u r e 7 . r - d n l 9 - b i t r d ac ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 inl ( l sb) 64 48 16 32 0 8 0 9 6 1 1 2 128 code (decimal) 03615-0-006 t a = ? 40c, +25c, +85c superimposed v dd = 5v f i g u re 8. inl 7- bit r d a c ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 dnl (ls b ) 64 48 16 32 0 8 0 9 6 1 1 2 128 code (decimal) 03615-0-007 t a = ? 40c, +25c, +85c superimposed v dd = 5v f i g u re 9. dn l 7-b i t r d a c
adn2860 rev. 0 | page 9 of 2 0 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 r-inl (ls b ) 64 48 16 32 0 8 0 9 6 1 1 2 128 code (decimal) 03615-0-008 t a = ? 40c, +25c, +85c superimposed v dd = 5v f i g u re 10. r-inl 7 - bit r d a c ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 r-dnl (ls b ) 64 48 16 32 0 8 0 9 6 1 1 2 128 code (decimal) 03615-0-009 t a = ? 40c, +25c, +85c superimposed v dd = 5v f i g u re 11. r-dnl 7 -bit r d a c 0 5 10 15 20 25 30 35 40 45 50 rheostat mode te mp co (ppm/ c) 256 19 2 64 1 2 8 0 320 384 44 8 512 code (decimal) 03615-0-010 t a = ? 40c, +85c v dd = 5v v a = v dd v b = 0v f i gure 1 2 . t e m p er atur e co effici ent (r heo s ta t m o de) 0 5 10 15 20 25 30 35 40 45 50 p o te ntiome te r mode te mp co (ppm/ c) 256 19 2 64 1 2 8 0 320 384 44 8 512 code (decimal) 03615-0-011 t a = ? 40c, +85c v dd = 5v v a = v dd v b = 0v f i gure 13. t e mpe r a t ur e coeffi cie n t ( p o t enti om ete r m o de) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 s u p p l y curre nt (ma) ? 4 0 ? 20 0 2 0 4 0 6 0 8 0 100 120 140 temperature ( c) 03615-0-012 i dd : v dd = 5.5v i dd : v dd = 2.7v i s : v dd = 2.7v, v ss = 2.7v f i gure 14. sup p l y current v s . t e mper at ur e 30 40 50 60 70 80 i dd (ma) 90 100 110 11 0 1 10 2 10 3 10 4 10 5 10 6 10 7 clock frequency (hz) 03615-0-013 t a = 25c v dd = 5.5v v dd = 2.7v f i gure 1 5 . sup p l y current vs . cl ock f r equenc y
adn2860 rev. 0 | page 10 of 20 interf ace descriptions i 2 c interf a c e a l l con t r o l and acc e ss t o b o t h e e pro m m e mo r y and t h e r d a c r e g i st ers a r e cond uc te d v i a a st and a rd 2- w i re i 2 c in ter f ace . f i g u r e 2 sh o w s t h e timing c h a r ac t e r i s t ics o f th e i 2 c b u s. f i gur e 16 a nd f i gur e 17 i l l u st r a te st anda rd t r a n smi t and r e cei v e b u s sig n als in t h e i 2 c in t e r f ace . th e s e f i gur e s us e t h e fol l o w in g l e g e n d : f r o m mast er t o s l a ve f r om sl a v e to m a ste r s = s t a r t co n d i t io n p = s t o p co n d i t io n a = a c k n o w le dg e (s d a lo w) a = n o t ac k n o w ledg e (s d a hig h ) r/ w = re ad enab l e a t h i g h and wr i t e enab le a t lo w slave address s 0 = write a data a data transferred (n bytes + acknowledge) data a/a p 03615-0-016 r/w f i g u re 16. i 2 cm a st er t r ansmi tti ng d a ta to sl a v e slave address s 1 = write a data a data transferred (n bytes + acknowledge data a p 03615-0-017 r/w f i g u re 17. i 2 cm a s t er r e ading d a t a f r o m s l ave slave address s read or write a data (n bytes + acknowledge) a/a p 03615-0-018 r/w slave address s read or write repeated start a data (n bytes + acknowledge) a/a r/w direction of transfer may change at this point f i gu r e 1 8 . c o m b in ed t r a n smi t / r ea d
adn2860 rev. 0 | page 11 of 20 eeprom interf a c e memory address memory data memory data sa a a a a 00 0 1 e e 0 01 1 p 03615-0-019 0 write (n bytes + acknowledge) eeprom slave address a/a f i g u re 19. e e p r o m w r i t e memory data memory data sa a a a 00 0 1 e e 0 01 1 p 03615-0-020 1 read (n bytes + acknowledge) eeprom slave address a f i gure 20. e e p r o m current r e ad slave address memory address s 0 write aa p 03615-0-021 w slave address memory data sr 1 read repeated start a (n bytes + acknowledge) a/a f i g u re 21. e e p r o m rand om r e ad the 256 b t e s of eep r o m m e m o r p r o v ided in t h e ad n286 0 a r e o r ga nie d in t o 16 p a g e s o f 16 b t e s eac h . the o r d sie o f e a ch me mor l o c a t i o n i s o n e b te i d e . the i 2 c sla v e addr es s o f th e ee p r o m is 10100 (a1e)(a0e), h er e a1e and a0e a r e et e r n al p i n p r og ra mma b l e addr es s b i ts. t h e 2pin p r o g r a mma b l e addr ess b i t s a l lo a to t a l o f fo ur ad n2860 de vic e s t o be con t r o l l ed b a sin g le i 2 c mas t er b u s, ea c h ha vi n g i t s o n eep r o m. a n i n te r n a l 8 bit a ddre s s c o u n te r for t h e e e p ro m i s a u t o ma tical l incr em en t e d f o l l o in g eac h r e ad o r r i t e o p era t ion. f o r r e ad o p er a t io n s , t h e addr es s co u n t e r is i n cr em en t e d a f t e r ea c h b t e i s r e a d , a n d t h e co un t e r r o ll s o v e r f r o m a ddr es s 2 55 t o 0. f o r r i t e o p er a t io n s , t h e addr ess co un t e r is i n crem e n t e d a f t e r e a ch b t e is r i t t e n. th e co un t e r r o l l s o v er f r o m t h e hig h est addr es s o f t h e c u r r en t p a g e t o t h e lo e s t addr es s o f t h e c u r r en t p a ge. f o r e a m ple, r i t in g t o b tes b e g i nn in g a t a ddr ess 31 ca us es t h e co u n t e r t o r o l l b a ck to a ddr ess 16 a f ter t h e f i rst b t e is r i t t e n t h e n t h e addr es s i n crem e n ts t o 17 a f ter t h e s e cond b te i s r it te n. eeprom write e a ch wr i t e o p er a t io n i s s u e d t o t h e eepr o m p r og ra m s e t w e e n t e an d t e s p a g e o f m e m o r i gur e s h o w s t h e eep r o m wr i t e in t e r f ace the n u m er o f t e s o f da t a t h a t t h e us er wan t s to s e nd t o t h e e e p r o m is unr e s t r i c t e d i f m o r e t h a n t e s o f da t a a r e s e n t in a sin g le wr i t e op era t ion t h e addr ess co u n ter r o l l s a ck to t h e e g i nn in g ad d r ess a nd t h e pre i ou sl s e n t d a t a i s oe r w r itte n eeprom writ e-acknowledge polling af t e r e a ch wr i t e o p era t ion a n i n t e r n al eep r o m wr i t e c cle e g i n s d u r i n g t h e eepr o m in ter n al wr i t e c cle t h e i c in ter f ace o f t h e de ice is dis a l e d i t is ne cess a r to deter m i n e if t h e i n t e r n al wr i t e c cle is co m p let e an d w h et h e r t h e i c in t e r f ace is e n a le d t o do s o ee c u t e i c in t e r f ace p o l l in g s e ndin g a st a r t co ndi t i on fol l o w e d t h e eepro m sl a e addr ess pl us t h e desir e d r w i t i f th e ad i c in ter f ace r e s p o n ds w i t h an a c t h e wr i t e c cle is co m p let e an d t h e in t e r f ace is r e a d t o p r o c e e d wi t h f u r t h e r o p era t io n s o t h e r w is e th e i c i n t e r f a c e m u st e p o l l e d ag ai n to d e te r m i n e w h e t he r t h e wr i t e c cle has e e n com p let e d eeprom read the ad eep r o m p r o ides tw o dif f er en t r e ad o p er a t io ns sh ow n in i gur e a nd i gur e the n u m er o f t e s r e ad f r o m t h e eeprom in a si n g le o p era t io n is unr e s t r i c t ed i f m o r e than t e s a r e r e ad t h e addr es s co un ter r o l l s a ck to t h e st a r t a ddr ess an d d a t a p r e io usl r e ad i s re a d ag ai n i gur e s h o w s t h e eep r o m c u r r en t r e ad o p e r a t io n this o p er a t ion do es n o t a l lo w an ad dr ess lo ca t i o n to e sp e c if ie d a nd r e ads da t a e g i nni n g a t t h e c u r r en t addr ess lo ca t i on sto r e d in t h e i n t e r n al addr es s co un t e r
adn2860 rev. 0 | page 12 of 20 a ra ndo m r e a d o p era t ion is sh o w n in f i gur e 21. this o p er a t io n cha n g e s t h e addr es s co un t e r t o t h e sp e c if ie d m e m o r y addr es s b y pe rf o r m i n g a du m m y w r i t e and t h e n p e r f o r min g a r e ad o p er a t ion b e g i n n in g a t t h e ne w addr ess co u n ter lo ca t i on. eeprom write protection se t t i n g th e wp p i n t o a log i c lo w p r o t e c ts t h e eep ro m me mor y f r om f u tu re w r i t e op e r a t i o ns . in t h i s m o d e , e e p rom r e ad o p era t io n s a nd r d a c r e g i s t er lo adin g o p e r a t e n o r m al l y . rd a c i 2 c interf a c e data data sa a a a a 10 0 0 1 r ee/ rd a 4 a 3 a 2 a 1 a 0 ac cmd/ reg r 1 10 0 p 03615-0-022 0 write (n bytes + acknowledge) rdac address rdac slave address a/a f i gure 22. r d a c wr ite sa a a 11 0 1 r a rdac eeprom or register data rdac eeprom or register data r 1 10 0 p 03615-0-023 1 read (n bytes + acknowledge) rdac slave address a f i gure 23. r d a c cu rr e n t r e ad slave address rdac address s 0 write aa p 03615-0-024 w slave address rdac data sr 1 read repeated start a (n bytes + acknowledge) a/a f i gur e 2 4 . rd a c random re a d sa a a 10 0 1 r c 1 c 2 c 3 c 0 a 2 a 1 a 0 cmd/ reg r 1 10 0 p 03615-0-025 a 0 write 1 cmd rdac slave address f i g u re 25. r d a c sh or tcut co mm ands tab l e 5. rdac register ad d r esses (cmd/ reg = 0, ee/ rdac = 0) a 4 a 3 a 2 a 1 a 0 r d a c b y te descriptio n 0 0 0 0 0 r d a c 0 (d7)(d 6)(d5 )(d4 )(d 3)(d2)(d1)(d 0) C rdac 0 8 ls bs 0 0 0 0 1 rdac0 (x) ( x) (x) ( x )(x )( x )(x )(d8 ) C rd ac 0 msb 0 0 0 1 0 r d a c 1 (d7)(d 6)(d5 )(d4 )(d 3)(d2)(d1)(d 0) C rdac 1 8 ls bs 0 0 0 1 1 rdac1 (x) ( x) (x) ( x )(x )( x )(x )(d8 ) C rd ac 1 msb 0 0 1 0 0 r d a c 2 (x)(d6)(d5)(d4)( d3)(d2 )(d1) (d0) C rdac2 7 bits 0 0 1 0 1 r e s e r v e d t o 1 1 1 1 1
adn2860 rev. 0 | page 13 of 20 table 6. rdac r/ w eeprom addresses (cmd/ reg = 0, ee/ rdac = 1) a4 a3 a2 a1 a0 byte description 0 0 0 0 0 rdac0 8 lsbs 0 0 0 0 1 rdac0 msb 0 0 0 1 0 rdac1 8 lsbs 0 0 0 1 1 rdac1 msb 0 0 1 0 0 rdac2 7 bits 0 0 1 0 1 11 bytes rdac user eeprom to 0 1 1 1 1 table 7. rdac command table (cmd/ reg = 1) c3 c2 c1 c0 command description 0 0 0 0 nop 0 0 0 1 restore eeprom to rdac 1 0 0 1 0 store rdac to eeprom 2 0 0 1 1 decrement rdac 6 db 0 1 0 0 decrement all rdacs 6 db 0 1 0 1 decrement rdac 1 step 0 1 1 0 decrement all rdacs 1 step 0 1 1 1 reset. restore eeprom to all rdacs 2 1 0 0 0 increment rdac 6 db 1 0 0 1 increment all rdacs 6 db 1 0 1 0 increment rdac 1 step 1 0 1 1 increment all rdacs 1 step 1 1 0 0 reserved to 1 1 1 1 1 command leaves the device in the eeprom read power state. i ssue the nop command to return the device to the idle state. 2 command requires acknowledg e polling after execution. rdac interface operation each programmable resistor wiper setting is controlled by specific rdac registers, as shown in table 5. each rdac register corresponds to an eeprom memory location, which provides nonvolatile wiper storage functionality. rdac registers and their corresponding eeprom memory locations are programmed and read independently from each other. the rdac register is refreshed by the eeprom locations either with a hardware reset via pin 1, or by issuing one of the various rdac register load commands shown in the table 7. rdac write setting the wiper position requires an rdac write operation, shown in figure 22. rdac write operations follow a format similar to the eeprom write interface. the only difference between an rdac write and an eeprom write operation is the use of an rdac address byte in place of the memory address used in the eeprom write operation. the rdac address byte is described in detail in table 5 and table 6. as with the eeprom write operation, any rdac eeprom (shortcut command 2) write operation disables the i 2 c interface during the internal write cycle. acknowledge polling, as described in the eeprom interface section, is required to determine whether the write cycle is complete. rdac read the adn2860 provides two rdac read operations. the first, shown in figure 23, reads the contents of the current rdac address counter. figure 24 illustrates the second read operation, which allows users to specify which rdac register to read by first issuing a dummy write command to change the rdac address pointer, and then proceeding with the rdac read operation at the new address location. the read-only rdac eeprom memory locations can also be read by using the address and bits specified in table 6.
adn2860 rev. 0 | page 14 of 20 rdac shortcut comma n d s e l e v e n s h or tc ut shor tc ut c o m m and s are prov i d e d f o r e a s y ma ni p u la t i o n o f rd a c r e g i sters a nd t h eir co r r esp o n d i n g eep r o m m e mo r y lo ca t i o n s. th es e comman d s a r e s h own i n t a bl e 9 . a more d e t a i l e d d i s c u s s i on a b out t h e r d a c s h or tc ut co mman d s c a n b e fo u n d i n t h e the o r y o f o p era t io n s e c t ion. the i n te r f ac e for issu ing an r d a c shor tc u t c o mmand is show n in f i gur e 25. al l s h o r t c u t comma n ds r e q u ir e ackn o w ledge p o l l in g to deter m i n e w h et h e r t h e command ha s f i nishe d exe c u t in g. rdac resistor tolera nce th e e n d - to - e nd re s i st anc e tol e r a nc e for e a ch r d a c ch an nel i s store d i n re a d - o n l y me mor y d u r i ng f a c t or y pro d u c t i on . t h i s info r m a t io n is re ad b y usin g t h e addr ess and b i t s sp e c if ie d i n ta b l e 8 . t o leran c e val u e s a r e s t o r e d in p e r c en t a ge fo r m . f i gur e 26 s h o w s t h e fo r m a t o f t h e t o lera n c e da t a s t o r e d i n m e mo r y . e a ch s t o r e d t o lera n c e us es t w o m e m o r y lo ca t i o n s. the f i rs t lo ca t i on s t o r es t h e in teg e r p o r t io n, w h ile t h e s e co nd lo c a t i o n s t o r es t h e de c i ma l po r t i o n . the r e sis t an ce tolera n c e is st o r e d in sig n -ma g ni t u de fo r m a t . t h e ms b o f th e f i r s t m e m o r y loca ti o n d e si gna t e s th e si g n (0 = +, 1 = ? ) a nd t h e r e ma ining 7 ls bs a r e des i g n a t e d fo r t h e in teger p o r t io n o f t h e toler a n c e. a l l 8 b i ts o f t h e s e co nd m e m o r y lo ca t i on a r e r e p r es en t e d t h e de cimal p o r t io n o f t h e tol e r a nc e v a lu e. tab l e 8. add r esses for read i n g toleran c e (cmd/ reg = 0, ee/ rdac = 1, a4 = 1) a 4 a 3 a 2 a 1 a 0 d a t a b te desc riptio n 1 1 0 0 0 s i g n and 7-bit integer valu es of rdac0 tolerance (read-only) 1 1 0 0 1 8-bit decimal value of rdac0 to lerance (read-only) 1 1 0 1 0 s i g n and 7-bit integer valu es of rdac1 tolerance (read-only) 1 1 0 1 1 8-bit decimal value of rdac1 to lerance (read-only) 1 1 1 0 0 s i g n and 7-bit integer valu es of rdac2 tolerance (read-only) 1 1 1 0 1 8-bit decimal value of rdac2 to lerance (read-only) 7 bits for integer number sign sign 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a a d6 d5 d4 d3 d2 d1 d0 d7 2 ?2 2 ?1 2 ?3 2 ?4 2 ?5 2 ?6 2 ?7 2 ?8 a d6 d5 d4 d3 d2 d1 d0 d7 8 bits for decimal number 03615-0-026 f i gure 26. f o rm at o f sto r ed t o ler a nce i n sign m a gn itude with b i t p o s i ti on d e scri pt i o ns (uni t i s in %, o n l y d a ta bytes sho wn)
adn2860 rev. 0 | page 15 of 20 theor y of opera tion the adn2860 dig i t a l p o t e n t iom e t e r o p era t es as a tr ue va r i a b l e r e sis t o r . th e r d a c r e g i s t er co n t en ts det e r m i n e t h e r e sis t o r w i pe r pos i ti o n . t h e r d a c r e gis t e r a c t s l i k e a s c r a t c h p ad r e g i s t er , al lo wing unlimi t e d r e sis t an ce s e t t in g cha n g e s. rd a c r e g i s t er co n t en t s a r e cha n g e d usin g t h e adn28 60 s s e r i al i 2 c i n t e rf a c e . s e e th e r d a c i 2 c i n t e rf a c e secti o n f o r th e f o rm a t o f th e da ta w o r d s a n d co m m a n d s t o p r ogra m th e r d a c r e gi st e r s. e a ch rd a c r e g i s t er has a co r r es p o n d i n g eep ro m m e m o r y l o c a t i o n , w h i c h prov i d e s no n v o l a t i l e s t or age of re s i stor w i p e r p o si tio n s e t t in g s . th e adn286 0 p r o v ides co mma nds t o s t o r e t h e r d a c r e g i st er co n t e n ts t o t h eir r e s p e c t i v e eep r o m m e m o r y l o ca ti o n s . duri n g s u b s eq ue n t po w e r - o n seq u en ce s , t h e r d a c r e gi s t e r s a r e a u t o m a ticall y l o a d ed wi th t h e s t o r ed val u e s . sa vin g da t a f r o m a n rd a c reg i s t er t o eep r o m m e m o r y tak e s a p p r o x ima t e l y 25 m s an d con s u m es 35 ma. i n ad di t i on to m o vi n g da t a b e t w e e n r d a c r e g i sters an d e e p rom me m o r y , t h e a d n 2 8 6 0 prov i d e s ot h e r shor tc ut co mman d s. table 9. adn2 860 shortcut commands n o . f u n c t i o n 1 restore eeprom setting to rd ac 1 2. store rdac regi ster contents to eeprom 2 3 decrement rdac 6 db (s hift dat a bits right) 4 decrement all r d acs 6 d b ( s hift all d a ta bits righ t) 5 decrement rdac 1 step 6 decrement all r d acs 1 step 7 reset eeprom s e tting to rdac 2 8 increment rdac 6 db (shift dat a bits left) 9 increment all r d acs 6 d b ( s hift all d a ta bits left) 10 increment rdac 1 step 11 increment all r d acs 1 step __________________________ 1 c o mmand l e aves t h e d e vice in the eep ro m read p o wer state. is s u e the nop command to return the devi ce to the id l e s t ate. 2 c o mmand requires acknow l e d g e polling af ter execution. linear increment and decreme n t c o mmands the in cr em en t a nd decr em en t co mman d s (c omman d s 10, 11, 5 , and 6 ) are u s e f u l for l i ne ar ste p a d j u st me n t a ppl i c a t i o ns . th es e co mmands sim p lif y micr o c o n tr ol ler s o f t wa r e co din g b y all o w i n g th e co n t r o ll e r t o se n d o n l y a n in cr em en t o r d e cr em en t co mman d t o the adn2860. the ad j u s t m e n t c a n b e dir e c t ed t o a n in divid u al rd a c o r t o al l thr e e rd a c s. l o garithmic t a per mode adjust ment ( 6 db/step) the adn2860 acco mm o d a t es l o ga r i thmic ta p e r ad j u s t m e n t o f th e rd a c wi per posi ti o n (s) b y s h i f ti n g th e r e gis t e r co n t e n t s lef t /r ig h t fo r in c r em e n t/ de cr e m en t o p er a t io ns. c o mman d s 8, 9, 3, a n d 4 a r e used t o l o ga ri th m i call y i n cr em e n t o r d e cr e m en t t h e w i pe r pos i ti o n s i n d i v i d u all y o r c h a n g e all th r ee c h a n n e l set t in gs a t t h e s a me t i me. i n cr em en ti n g th e wi pe r posi ti o n b y +6 d b d o ub le s th e r d a c r e g i s t er val u e , w h i l e de cr e m en t i n g b y ?6 db halv es i t . i n t e r n al l y , th e ad n2860 u s es a s h if t r e g i s t er t o s h if t t h e b i ts lef t an d r i g h t t o a c h i ev e a l o ga ri th m i c in cr em en t o r d e cr em e n t . n o n i d e al 6 db s t ep ad j u s t m e n t o c curs un der cer t a i n co n d i t io n s . t a b l e 10 ill u s t ra t e s h o w t h e sh i f ti n g fun c ti o n a f f e ct s th e da ta b i ts o f a n i ndivi d u a l rd a c . e a ch col u mn goin g do wn t h e t a b l e r e p r es en ts a s u c c es si v e s h if t o p e r a t io n. n o t e t h a t t h e lef t -s hif t co mman d s (c omman d s 10 and 11) w e r e m o dif i e d such t h a t if t h e da t a in t h e rd a c r e g i st er e q uals 0 an d t h e da t a is shif te d , t h e r d a c r e g i st er is s e t t o c o de 1. simi la rl y , if t h e da t a in t h e rd a c r e g i st er is g r ea t e r tha n or eq ual t o mids c a le a nd t h e da ta is lef t shif t e d , t h e d a t a in t h e rd a c r e g i st er is a u t o ma t i ca l l y s e t t o fu l l - sc a l e . t h i s m a k e s th e l e ft - s h i ft fu n c t i o n a s c l o s e a s p o s s i b l e t o a loga r i t h mic ad j u st m e n t . the r i g h t - shif t co mman d s (c omman d s 3 and 4) a r e ide a l o n ly i f th e l s b i s a 0 (i d e al loga ri th m i c = n o e r r o r). i f th e l s b i s 1, t h e r i g h t-sh if t f u n c t i on ge n e ra tes a li n e a r ha lf ls b er r o r . table 10. rda c register contents after 6 d b step a d justmen t s left shift (+6 db/step) right shift (?6 db/step) 0 0000 0000 1 1111 1111 0 0000 0001 0 1111 1111 0 0000 0010 0 0111 1111 0 0000 0100 0 0011 1111 0 0000 1000 0 0001 1111 0 0001 0000 0 0000 1111 0 0010 0000 0 0000 0111 0 0100 0000 0 0000 0011 0 1000 0000 0 0000 0001 1 0000 0000 0 0000 0000 1 1111 1111 0 0000 0000 1 1111 1111 a c t u al co nfo r ma n c e t o a loga r i t h mic c u r v e b e t w e e n t h e da t a co n t e n ts i n t h e rd a c r e g i st er a nd t h e wi p e r p o si t i o n fo r e a ch r i g h t-sh if t co m m a nd (c o mman d s 3 and 4) exe c u t io n con t ains a n er r o r o n l y fo r o dd n u m b ers o f b i ts. e v e n n u m b ers o f b i ts a r e i d e a l. f i g u re 2 6 show s a pl ot of l o g _ e r ror , t h a t i s , 2 0 l o g10(er r o r/co de), f o r th e adn2860.
adn2860 rev. 0 | page 16 of 20 using additional internal nonv ol a t ile eeprom the adn2860 co n t a i n s addi tional in ter n al us er eep r o m f o r s a v i ng c o nst a n t s an d ot he r d a t a . t h e u s e r e e p r o m i 2 c da t a wo r d fol l o w s t h e s a me fo r m a t a s t h e ge ner a l - p u r p o s e e e p ro m m e m o r y s h own in f i gur e 19 and f i gur e 20. u s er eep r o m m e m o r y addr ess e s a r e sh o w n i n t a b l e 6. t o supp or t t h e u s e of m u lt ipl e e e p rom mo du l e s on a s i ng l e i 2 c b u s, th e adn2860 f e a t ur es tw o ext e r n al addr es sin g p i n s , p i n s 21 an d 22 ( a 1_ee an d a0_ ee) t o ma n u al l y s e t the addr ess o f th e eep r o m in c l uded wi t h the adn2860 . this f e a t ur e e n s u r e s th a t t h e co rr ect eep r o m m e m o r y i s a cce s s e d w h en u s i n g m u lt i p l e me mor y mo d u l e s on a s i ng l e i 2 c b u s. digit a l input/output c o nfigur a t ion all d i gi tal i n p u ts a r e es d p r o t e c t e d . d i g i tal in p u t s a r e h i g h im p e d a n c e and ca n b e dr i v en di r e c t ly f r o m m o st dig i t a l s o ur ces. the res e t dig i t a l i n pu t p i n do es n o t ha ve an i n ter n a l p u l l -u p r e sis t o r . th er efo r e , t h e us er sh ou ld place a p u l l - u p r e sis t o r f r o m res e t to v dd i f th e fun c ti o n i s n o t us ed . th e wp pi n h a s an in ter n a l p u l l - d o w n r e sisto r . i f no t dr i v en b y an ex ter n a l s o ur ce, th e ad n2860 defa u l ts t o a wr i t e-p r o t ec ted sta t e . es d p r o t ec tion o f th e dig i tal in p u ts is sh o w n in f i gur e 27. wp inputs v dd gnd 03615-0-027 f i g u re 27. equiv a le nt wp e s d p r ot ec t i on mul t iple de vices on one bus f i gur e 28 s h o w s f o ur ad n2860 de vices on the s a me s e r i al b u s. e a ch has a dif f er en t s l a v e addr e s s b e c a us e t h e st a t e o f t h eir ad 0 a nd a d 1 p i n s ar e dif f er en t. thi s a l lo ws in dep e n d e n t r e a d in g a nd wr i t in g t o e a ch r d a c wi t h in e a ch d e vi ce . +5v r p r p master sda sda ad1 ad0 scl sda ad1 ad0 scl sda ad1 ad0 scl sda ad1 ad0 scl scl v dd v dd v dd 03615-0-028 f i g u re 28. m u lt ip le a dn28 6 0 d e v i ces on a s i ng l e bus level shift for bidirec t ional c o mmunic a tion w h ile m o s t legac y sys t em s o p er a t e a t on e v o l t a g e , adding a ne w co m p on e n t mig h t r e q u ir e a dif f er en t v o l t a g e . w h e n tw o systems t r a n smi t t h e s a m e sig n a l a t two dif f er en t v o l t ag es, us e a le v e l sh i f te r to a l l o w t h e s y st e m s to c o mm u n i c a t e. f o r exa m p l e , a 3.3 v micr o c o n t r ol ler ( m cu) can b e us ed alo n g wi t h a 5 v dig i t a l p o t e n t iom e t e r . a le v e l sh if t e r is r e q u ir e d t o ena b le b i dir e c t i o na l co mm u n ic a t io n. f i g u re 2 9 show s one of m a n y p o ss ibl e te c h n i qu e s to prop e r ly le v e l -s hif t sig n a l s betwe e n tw o de vices. m1 and m2 a r e n-c h ann e l fet s (2n7002). i f v dd fal l s be lo w 2.5 v , us e lo w thr e s h old n-c h a nne l fet s (fd v 301n) f o r m1 a nd m2. v dd1 = 3.3v v dd2 = 5v sda1 scl1 sda2 scl2 r p r p r p r p g g s s d d m1 m2 3.3v mcu 5v adn2860 03615-0-029 f i gure 29. l e vel s h i f ting for d i fferent v o ltag e d e v i ces o n an i 2 c bus terminal vol t a g e o p e r a t ion r a nge the adn2860 p o si ti v e v dd a nd n e ga t i ve v ss p o we r - su p p ly in p u ts def i n e t h e b o u nda r y co ndi t i on s fo r p r o p er 2-ter m ina l p r og ra mma b l e r e sis t a n c e o p era t io n. s u p p l y sig n als o n t e r m ina l s w a n d b th a t e x ceed v dd or v ss are cl am p e d b y t h e i n te r n a l f o r w a r d-b i as e d dio d es o f the ad n2860. v dd v ss a w b 03615-0-030 f i g u re 30. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and v ss the g r o u nd p i n o f t h e adn286 0 is us e d as a di g i t a l g r o u nd r e f e r e n c e , a n d n eed s t o be ti e d t o th e co mm o n gr o u n d o f th e pcb . ref e r e n c e th e dig i t a l in p u t co n t r o l sig n als t o th e ad n286 0 gr o u n d p i n , a n d sa ti sf y th e logi c lev e l s d e f i n e d in th e electri c al ch a r a c t e ri s t i c s ta b l e s .
adn2860 rev. 0 | page 17 of 20 power-up sequence sin c e t h e es d pr o t e c t i o n di o d e s limi t t h e v o l t ag e co m p l i an ce a t t h e a, b , an d w t e r m ina l s (f igur e 30), i t is im p o r t a n t t o p o w e r v dd /v ss bef o r e a p p l yin g an y v o l t a g e t o th e a, b , a nd w t e r m ina l s. o t h e r w is e , t h e dio d e is fo r w a r d-b i as e d such t h a t v dd /v ss a r e po w e r e d un in t e n t io n a ll y , wh i c h a f f e ct s th e r e s t o f t h e cir c ui t. th e ide a l p o w e r - u p s e q u e n ce is as fol l o w s: gnd , v dd , v ss , dig i t a l in p u ts, a nd v a/ b / w . t h e ord e r of p o we r i ng v a , v b , v w , a n d t h e dig i t a l in p u ts is n o t i m p o r t a n t a s lo n g as t h e y are p o we re d af t e r v dd /v ss . l a y o ut an d power s u ppl y biasi n g i t is a l wa y s a go o d p r ac t i ce t o us e co m p ac t, mi nim u m le ad len g t h l a yo u t de sig n . m a k e t h e l e ads t o t h e in p u t as dir e c t as pos s i b le wi th a m i n i m u m co n d uct o r le n g th . m a k e s u r e th a t g r o u n d p a t h s ha v e lo w r e sis t ance an d lo w ind u c t a n c e . s i mil a rl y , i t is al s o g o o d p r ac tic e t o b y p a s s the p o w e r s u p p lies wi t h q u ali t y ca p a ci t o rs. u s e lo w eq ui valen t s e r i es r e sis t a n c e (es r ) 1 f t o 10 f ta n t al u m or e l ec tr ol ytic ca p a ci t o rs a t t h e s u p p lies t o mi ni mi ze an y t r a n si en t di s t urb a n c e a nd f i l t er lo w f r e q u e nc y r i p p l e . f i g u re 3 1 i l l u st r a te s t h e b a s i c su p p ly - b y p a s s in g co nf igura t io n f o r th e ad n2860. v dd v ss v dd v ss gnd adn2860 c3 c4 c1 c2 + + 10 f 10 f 0.1 f 0.1 f 03615-0-031 f i g u r e 3 1 . p o w e r su pp l y by pa s s i n g s o l d er t h e sl u g on t h e b o t t o m o f t h e lf csp p a cka g e t o a f l o a t i n g p a d to im p r o v e t h er ma l diss i p a t io n. d o n o t co n n e c t t h e sl ug to a g r o u n d plan e o n t h e pcb . rd a c str u c t ure t h e p a t e n t p e n d i ng r d a c c o n t ai ns a st r i ng of e q u a l re s i stor s e g m en ts, w i t h a n a r ra y o f a n alog swi t ch es. the sw i t ch es ac t as th e wi pe r co nn e c ti o n . the adn2860 has tw o rd a c s wi t h 512 co nn e c tio n p o in ts a l l o w i ng i t to prov i d e b e tte r t h a n 0 . 2 % s e t - a b i l i t y re s o lut i on. the adn2860 als o co n t a i ns a t h ir d rd a c wi t h 128-s t ep re s o lut i on . f i g u re 3 2 show s an e q u i v a l e n t s t r u c t u r e of t h e c o n n e c t i ons betw een t h e two t e r m inals tha t mak e u p o n e cha n n e l o f a n rd a c . th e s w b sw i t ch is al wa ys o n , w h i l e on e o f t h e s w i t ch es, sw(0) t o sw(2 n ? 1), m a y o r m a y n o t be o n a t a n y gi v e n tim e d e pen d i n g o n th e r e si s t a n ce posi ti o n decod e d f r o m th e da t a b i ts in t h e r d a c r e g i st er . si nce t h e s w i t ches a r e noni de al , t h ere i s a 1 00 ? w i p e r r e si st anc e , r w . w i p e r re s i st anc e is a f u nc t i on of su p p ly vol t age and te m p - era t ur e; lo w e r s u p p l y v o l t a g es and hig h er t e m p era t ur es r e s u l t in hig h er wi p e r r e sis t a n ces. c o n s idera t ion o f wi p e r r e sis t a n ce d y na mi cs is i m p o r t a n t i n a p pli c a t ion s i n w h ich acc u ra te pre d i c t i on of output re s i st a n c e i s re qu i r e d . 03615-0-032 rdac wiper register and decoder digital circuitry omitted for clarity r s = r ab /2 n r s r s r s a x w x b x sw b sw(0) sw(1) sw(2 n ?1 ) sw(2 n ?2 ) sw a f i gure 32. equiv a le nt r d a c struc t ure c a l c ul a t ing the progr a mmable resist ance the n o minal r e sis t a n ce o f t h e rd a c b e tw e e n t h e a and b t e r m inals is a v ai la b l e in 25 k? or 250 k?. th e f i nal tw o o r thr ee dig i t s o f t h e p a r t n u m b er det e r m in e t h e n o mi nal r e sis t a n c e val u e , f o r exa m p l e , 25 k? = 25 a nd 250 k? = 2 50. t h e f o l l ow i n g d i s c u s s i on d e s c r i b e s t h e c a l c u l a t i o n of re s i st anc e r wb (d) a t dif f er en t co des o f a 2 5 k? p a r t fo r r d a c 0. th e 9- b i t d a t a w o rd i n t h e rd a c la tch is de co de d to s e le c t o n e o f t h e 51 2 pos s i b l e set t i n gs . th e f i r s t wi pe r co nn ecti o n s t a r t s a t th e b t e r m inal f o r da ta 0 x 00 0. r wb (0) is 100 ? o f th e wi p e r r e sis t an ce and i t is in dep e n d en t o f th e full- s cale r e si s t a n ce . th e s e co n d co nn ecti o n i s th e f i r s t t a p p o in t w h er e r wb (1) becom e s 48 .8 ? + 100 = 14 8.8 ? f o r da ta 0x001. th e third co nn ec tion is th e n e xt t a p p o in t r e p r es en tin g r wb (2) = 97.6 + 100 = 197.6 ? f o r da t a 0x002, and s o o n . e a c h ls b da t a -va l ue in cr eas e m o v e s th e wi p e r u p t h e r e sis t o r ladder u n t i l th e la s t ta p po i n t i s r e a c h e d a t r wb (511) = 25,051 ?. s e e f i gur e 32 f o r a sim p lif i e d dia g ram o f th e e q ui va len t rd a c cir c ui t. th e s e g e n e ral e q ua t i o n s de t e r m i n e t h e p r og ra mme d o u t p ut r e sist a n c e b e twe e n w an d b .
adn2860 rev. 0 | page 18 of 20 f o r rd a c 0 a n d rd a c 1: () w ab wb r r d d r + = 512 ( 1 ) fo r r d a c 2 : () w ab wb r r d d r + = 128 (2) w h er e d is t h e de cima l e q ui va l e n t o f t h e d a t a c o n t a i ne d i n t h e rd a c r e g i ster a nd r w is t h e w i p e r r e sist a n c e . the o u t p u t r e sist a n ce val u es i n t a b l e 11 a r e s e t fo r t h e g i v e n rd a c l a t c h co des w i t h v dd = 5 v , whic h a p p l ies t o r ab = 25 k? di g i t a l p o te n t i o me te rs . table 11. r wb at selected co de s for r wb_fs = 2 5 k? d (de c ) r wb (d) (?) output state 5 1 1 2 5 0 5 1 f u l l s c a l e 2 5 6 1 2 6 0 0 m i d s c a l e 1 1 4 8 . 8 1 l s b 0 100 zero scale (wipe r contact resistance) n o t e tha t in t h e zer o -s cale con d i t io n, a f i ni te wi p e r r e sis t a n c e of 100 ? is p r es en t. t o a v o i d deg r ada t io n o r p o s s i b le des t r u c t io n o f th e i n t e rn al sw i t c h e s , ca r e s h o u l d be tak e n t o li m i t th e cu rr e n t f l ow b e t w e e n w and b to no more t h an 2 0 m a i n te r m it te n t ly or 2 ma con t in uo us l y . c h a n n e l - to -channel r wb m a tch i ng i s b e tte r t h a n 0 . 1 % . t h e change i n r wb wi t h t e m p era t u r e has a 35 p p m/c t e m p era t ur e c o e ffi c i e n t . l i k e t h e me chanical p o t e n t iomet e r t h a t t h e rd a c r e places, t h e ad n2860 p a r t s a r e t o tal l y symm etr i cal . th e r e sis t a n ce betw een th e w w i p e r a n d th e a t e rm i n a l also p r od uce s a d i g i tall y co n - tr ol le d co m p le m e n t a r y r e sis t a n ce , r wa . w h e n r wa is us ed , th e b t e rm i n a l ca n be f l oa ti n g o r ti ed t o th e w i pe r . se t t i n g th e r e s i s t a n ce val u e fo r r wa s t a r ts a t a maxim u m val u e o f r e sis t an ce and d e cr ea se s a s t h e da ta l o a d e d in th e l a t c h i s in cr e a sed i n v a l u e . the g e n e ral t r an sfer e q ua t i on s fo r t h is o p era t ion a r e as fol l o w s: f o r rd a c 0 a n d rd a c 1: () w ab wb r r d d r + ? = 512 512 ( 3 ) fo r r d a c 2 : () w ab wb r r d d r + ? = 128 128 ( 4 ) f o r exa m ple , t h e fol l o w in g rd a c la t c h co des s e t t h e co r r es p o n d in g o u t p ut r e sis t an c e val u es, w h ich a p pl y t o r ab = 25 k? dig i tal p o t e n t iom e ters. ta bl e 12 . r wa ( d ) at se lect e d co des fo r r ab = 25 k ? d (de c ) r wa (d) (?) output state 5 1 1 1 4 8 . 8 f u l l s c a l e 2 5 6 1 2 6 0 0 m i d s c a l e 1 2 5 0 5 1 1 l s b 0 2 5 1 0 0 z e r o s c a l e th e ty p i ca l d i s t r i b u tio n o f r ab f r o m c h anne l - to-c hanne l is 0 .1 % w i th i n th e s a m e pa c k a g e . dev i ce - t o - d e v i c e m a t c h i n g i s p r oc e s s lo t-dep e nden t , wi t h a wo rst- ca s e va r i a t io n o f 15%. r ab te m p - era t ur e co ef f i cie n t is 35 p p m/ c . progr a mm ing te po tent iome t e r divi der voltage o u tp ut ope r ation th e di g i t a l p o te n t i o me te r c a n b e c o nf i g u r e d to ge ne r a te a n output vo lt ag e at t h e w i p e r te r m i n a l , w h i c h i s pr op or t i on a l to t h e i n p u t vol t a g es a p plie d to t h e a and b ter m i n a l s. c o nn e c t i ng t h e a te r m i n a l t o 5 v and t h e b te r m i n a l to g r ou nd pro d u c e s a n o u t p ut v o l t a g e a t t h e w i p e r w h ich can va r y b e twe e n 0 v t o 5 v . e a ch ls b o f v o l t a g e is e q ual t o t h e v o l t a g e a p plie d acr o s s t h e a a nd b ter m in a l s di v i de d b y t h e 2 n p o s i t i on re s o lut i on of t h e p o te n t i o me te r d i v i d e r . s i n c e t h e adn2 860 ca n op era t e f r o m d u al su p p lies, th e g e n e ral eq ua ti o n s de f i n i n g th e o u t p u t v o l t a g e a t v w wi t h r e sp e c t t o g r o u n d fo r a n y g i ven i n p u t volt a g es a p pli e d to t h e a and b t e r m inals a r e as fol l o w s: f o r rd a c 0 a n d rd a c 1: () b ab w v v d d v + = 512 ( 5 ) fo r r d a c 2 : () b ab w v v d d v + = 128 ( 6 ) eq ua ti o n 5 as s u m e s tha t v w is b u f f er e d s o t h a t t h e ef fe c t o f wi pe r r e s i s t a n ce i s n u lle d . o p e r a t i o n o f th e d i gi tal po t e n t io m e t e r in t h e d i v i der mo de r e su l t s i n mo r e acc u r a te o p er a t io n o v er t e m p e r a t ur e . i n th i s m o d e , th e o u t p u t v o l t a g e i s d e pen d en t o n th e ra ti o o f th e in t e rn al r e si s t o r s, n o t o n t h e a b s o l u t e v a l u e ; t h er efo r e , t h e dr if t im p r o v es t o 15 p p m / c. th e r e is n o v o l t a g e p o la r i ty r e st r i c t i o n b e twe e n t h e a, b , a nd w ter m ina l s as lo n g a s t h e ter m inal v o l t a g e (v te rm ) s t a y s wi thin v ss < v te rm < v dd .
adn2860 rev. 0 | page 19 of 20 appli c a t ions l a ser dio d e driver (l dd ) c a libr a t io n the adn2860 ca n be us e d wi t h an y las e r dio d e dr i v er . i t s hig h re s o lut i on , c o m p a c t f o otpr i n t , a n d sup e r i or te m p e r atu r e d r i f t c h a r act e r i s t ics mak e i t id eal f o r o p tical p a ramet e r set t in g. the adn2841 is a 2.7 gb ps las e r dio d e dr i v er t h a t us es a uniq ue co n t r o l alg o r i t h m t o mana g e b o t h t h e las e r a v era g e po w e r a n d e x tin c ti o n ra ti o a f t e r i n i t i a l fa ct o r y cali b r a t i o n . i t s t ab il izes t h e l a s e r da t a t r a n smission b y c o n t in u o us l y moni to r i ng i t s o p tical po w e r a n d b y co rr ecti n g th e v a ria t i o n s ca us ed b y t e m p era t ur e and t h e las e r deg r ada t ion o v er t i m e . i n t h e ad n2841, the i mp d m o ni t o rs t h e las e r dio d e c u r r en t. thr o ug h i t s d u al- l oo p po w e r a n d e x tin c tio n ra ti o co n t r o l , cali b r a t ed b y th e ad n2860, t h e in t e r n al dr i v er co n t r o ls th e b i as c u r r en t i bi a s a nd co n s e q uen t l y t h e a v er a g e p o w e r . i t als o r e gu la t e s t h e mo d u - la ti o n c u rr en t, i modp , b y c h a n gi n g th e m o d u la ti o n cu rr e n t li n e a r l y wi t h s l o p e ef f i cien c y . a n y cha n ges in t h e l a s e r t h r e s h old c u r r en t o r s l o p e ef f i cienc y a r e , t h er efo r e , co m p en s a te d . a s a r e s u l t , t h is o p ti cal s u pe r v i s o r y sys t e m m i n i m i z e s th e lase r c h a r a c t e ri za ti o n ef fo r t s, ena b lin g desig n ers t o a ppl y co m p a r a b le las e rs f r o m mu l t i p l e s o u r c e s . adn2860 adn2841 sda scl pset erset aset v cc v cc 03615-0-033 f i g u re 33. o p t i c a l s u per v is or y sy s t e m
adn2860 rev. 0 | page 20 of 20 outline dimensions 1 24 6 7 13 19 18 12 2.25 2.10 sq 1.95 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indica t o r to p view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.25 min exposed pad (bottom view) compliant t o jedec st and ards mo-220-v ggd-2 f i gure 34. 2 4 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p ] 4 mm 4 m m b o d y (c p - 2 4 ) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature range package descri ption package option full container q u a n t i t y r ab (k?) adn2860acpz2 5 1 ?40c to +85c lead frame chip scale package cp-24 75 25 adn2860acpz2 5-rl7 1 ?40c to +85c lead frame ch ip scale package cp-24 1,500 25 adn2860acpz2 50 1 ?40c to +85c lead frame chip scale package cp-24 75 250 adn2860acpz2 50-rl7 1 ?40c to +85c lead frame ch ip scale package cp-24 1,500 250 adn2860-eval e v a l u a t i o n boar d 1 z = pb-free part. purch a se of li c e n s e d i 2 c com p on en t s o f an a l og d e vi ces or on e of i t s subli c en s e d as soci a t ed c o m p a n i e s con v eys a li cen s e for t h e purch a ser un der t h e ph i li p s i 2 c p a te nt rights to us e the s e co mpo n e nts in an i 2 c sy st em , provi d e d t h a t t h e syst em c o n f orm s t o t h e i 2 c stand a rd speci f ication as d e f i ned by phil ips . ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d03615-0-7/04(0)

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